Informatics Publishing Limited

Minal Saxena ¹, Kavita Khare ², Nilay Khare ³

Affiliations
1 Maulana Azad National Institute of Technology, Bhopal (M.P), IN
2 Electronics and Communication Department at Maulana Azad National Institute of Technology, Bhopal (M.P), IN
3 Computer Science and Engineering Department at Maulana Azad National Instt of Technology, Bhopal (M.P), IN

Abstract

The channel estimation techniques for OFDM systems based on pilot arrangement are investigated. The channel stimation based on comb type pilot arrangement is studied through different algorithms for both estimating channel at pilot frequencies and interpolating the channel. The estimation of channel at pilot frequencies is based on LS and LMS while the channel interpolation is linear interpolation, second order interpolation, low-pass interpolation, spline cubic interpolation, and time domain interpolation. Time-domain interpolation is obtained by passing to time domain through IDFT, zero padding and going back to frequency domain through DFT. In addition, the channel estimation based on block type pilot arrangement is performed by sending pilots at every sub-channel and using this estimation for a specific number of following symbols. We have also implemented decision feedback equalizer for all sub-channels followed by periodic block-type pilots. We have compared the performances of all schemes by measuring bit error rate with 16QAM, QPSK, DQPSK and BPSK as modulation schemes, and multipath Rayleigh fading and AR based fading channels as channel models. The simulation results show that combtype pilot based channel estimation with low-pass interpolation performs the best among all channel estimation algorithms.

Keywords

Channel Estimation, OFDM, Pilot Carrier, Rayleigh Fading.

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Deepak Kumar Patel ¹, Minal Saxena ¹

Affiliations
1 Department of Electronics & Communication, Sagar Institute of Research & Technology, Bhopal, IN

Abstract

High performance digital adder with less power consumption and reduced area is a fundamental design issues for advanced processors. Speed and area are now a days one of the important design issues in digital circuits. One of the fastest adder is Carry Select Adder (CSA) which is used in many processors to perform fast arithmetic function. To increase the efficiency of the adder many different adder architecture designs have been developed. As we know per second millions of operations are performed in microprocessors. So while designing of multipliers, speed of operation is one of most important criteria to be considered. Due to which faster multiplier and high speed architecture of adder plays an vital role in many applications. We, in this paper, proposed a technique for designing of FIR filter using urdhwa multiplier compressor and modified carry select adder. Verification of CSA structure is performed and implemented for 16, 32 and 64 bit filter circuits. Comparing with previous existing structure of adder and our proposed design improves the efficiency of adder. These designs are implemented on Xilinx software.

Keywords

Ripple Carry Adder (RCA), Carry Select Adder (CSA), Binary to Excess-1 Converter (BEC), Compressor, FIR Filter.

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